HPIPFTRAP-MIB: View SNMP OID List / Download MIB

This string provides a detailed description of the Event along with variable information.

The OS has registered an OS_INIT vector, but is has not passed the checksum

The OS has registered an OS_MCA vector, but it has not passed the checksum

The BMC has failed testing and has been disabled.

SFW failed to launch EFI

Monarch selection has failed. Data: 0x11 = Calibration Failure 0x22 = Select Code Failure

Monarch Collision has occurred

SFW attempted to virtualize EFI and failed

SFW was unable to virtualize PAL

SFW was unable to virtualize SAL

SFW was unable to virtualize SALPROC

SFW has failed initializing the CPU Struct. Data: Physical location of CPU that produced failure

A CPU has failed early config.

A CPU has failed early self test. Data: PAL Test State.

SFW has detected that a CPU has failed. Data: The Physical Location of the CPU that failed

SFW has determined a CPU or Memory has failed late test. This could be related to a CPU error or a Correctable Single Bit Memory error. Data: Physical location of CPU See Cause/Action.

The CPU late test has failed because of insufficient memory

Could not allocate memory for EFI image

EFI image is corrupted

EFI fit error

EFI NVM has failed testing. The cell or system will now halt.

EFI Image Error

EFI Image Error.

The IVT interrupting nesting depth has been exceeded. This processor will be halted. Data: Number of the offending vector.

An external interrupt has been requested and not serviced. Data: Number of the vector

An external interrupt has been taken. Data: Number of the vector taken.

Access to the FPL has failed.

SFW was unable to read the CPU PSR. Data: Physical location of CPU

SFW has halted the cell or system

SFW has determined that PAL is not compatible with the current processors.

SFW has determined that a slave processor is incompatible with the monarch. Data: Physical location of the incompatible processor.

Interrupt clear failed during cell config

SFW has determined that an IPMI event failed.

Data: interrupt vector table (IVT) Offset

LDB state bad

Interrupt context was lost. Data: interrupt number.

Registering of the processor min state save area with PAL has failed.

SFW has determined the monarch has timed out. SFW is deconfiguring the CPU. Data: Physical Location of CPU

A PAL_B FIT error has occurred

A SAL_B FIT error has occurred

NVM has failed test. The system will halt

A interrupt vector has been requested out of the acceptable range. Data: Vector Number.

The PAL Copy Info call has failed.

Error copying PAL to memory

A PAL Proc has failed. This will halt the processor. Data: Physical Location of CPU

A console device has failed. Data: Physical Addr of device that failed.

A console device has failed. Data: Physical Addr of device that failed.

Platform Scratch RAM has failed the test.

A CPU has failed to enter rendezvous. Data: Local CPU Number

SFW could not extract SAL_B from the ROM

Platform Scratch RAM has failed test.

IPMI SEL full

No wakeup vector registered for processor Data: Physical location of CPU

Slave Rendezvous handler has failed. Data: Physical Location of CPU

SFW failed to build the SMBIOS tables

The trap nesting limit has been exceeded. Data: Vector Number

A trap has been requested and not serviced. Data: Vector Number

A trap has been taken. Data: Number of the vector taken.

At least one interrupt was not cleared. Data: The highest pending interrupt number

An unexpected external interrupt has occurred. Data: External Interrupt Number

An interrupt has occurred before setting up the Interrupt Vector Table. Data: Interrupt Number

An unexpected MCA has occurred before MCAs are unmasked. Data: Local CPU Number.

An unexpected trap has occurred. The trap number is either invalid or the requested trap has not been registered. Data: Trap Number

SFW has detected an unknown error.

SFW has detected a PAL Failure

Expected Machine Check Vector not registered

This is the equivalent of a TOC event in the PA RISC Architecture. On IPF systems, this event is called an INIT. This event can be triggered by the 'tc' command from the MP, or from the button labeled 'TOC' :wor 'Transfer of Control' on the Management card or bezel of the system. There are also other causes of an INIT generated by software. Data: Local CPU Number

An I/O host bridge is missing. Firmware will continue boot and display the following EFI warning, 'Unexpected hardware I/O configuration.' Data Field: Physical location of the missing I/O host bridge.

Firmware detected an unexpected number of I/O slots connected to an I/O host bridge. Firmware display the following EFI warning message, 'Unexpected hardware I/O configuration.' Data Field: Physical location of the I/O host bridge.

Firmware found an I/O controller rope of unexpected width. Firmware will configure the I/O host bridge connected to the rope and display the following EFI warning message, 'Unexpected hardware I/O configuration.' Data Field: Physical location of the I/O host bridge connected to the rope.

Firmware found an unexpected I/O host bridge. Firmware will configure the I/O host bridge and display the following EFI warning message, 'Unexpected hardware I/O configuration.' Data Field: Physical location of the unexpected I/O host bridge.

An I/O host bridge's bus frequency DLL circuit failed. Firmware will deconfigure the failed I/O host bridge and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the I/O host bridge.

An I/O host bridge's hot-plug controller has failed. Firmware will deconfigure the I/O host bridge and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the I/O host bridge.

Firmware attempts to configure an I/O controller rope to an unsupported width. Firmware will deconfigure any I/O host bridge connected to the rope. Data Field: Physical location of the failed rope.

During I/O host bridge configuration, firmware found a persistent error condition. Firmware will deconfigure the I/O host bridge and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the I/O host bridge.

An I/O host bridge is inaccessible because an I/O controller rope reset failed to complete. Firmware will deconfigure the I/O host bridge and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the I/O host bridge.

There is insufficient power. Firmware will not power on a hot-plug I/O slot. In addition, firmware will display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Date Field: Physical location of the I/O slot.

Firmware encountered an unexpected error while attempting to configure an I/O host bridge's I/O devices. Firmware will continue boot but will not configure the I/O devices connected to the specified I/O host bridge. Such I/O devices will not be usable as console nor boot devices but might be usable by the O/S. Data Field: Physical location of the I/O host bridge.

The total resource requirement from the I/O devices connected to an I/O host bridge exceeds the resource limit of the I/O host bridge. Firmware will continue boot but will not configure the I/O devices connected to the specified I/O host bridge. In addition, firmware will display the following EFI warning message, 'Insufficient resources to assign to one or more I/O devices.' Such I/O devices will not be usable as console nor boot devices but might be usable by the O/S. Data Field: Physical location of the I/O host bridge.

Firmware encountered an unexpected error while attempting to clear resource allocations on an I/O host bridge's I/O devices. Data Field: Physical location of the I/O host bridge.

An I/O host bridge failed to determine the appropriate PCI[X] mode and frequency (PCI, PCI-X 66 MHz, PCI-X 133 MHz, etc.) for its bus. Firmware will deconfigure the I/O host bridge and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the failed I/O host bridge.

Firmware is unable to access the power monitor. Firmware will assume that there is sufficient power and proceed to power on an I/O slot. Data Field: Physical location of the I/O slot.

An I/O controller rope reset did not complete within the expected time limit. Firmware will deconfigure the I/O host bridge attached to the rope. Data Field: Physical location of the deconfigured I/O host bridge.

During I/O chipset configuration, firmware found a persistent error condition. Firmware will attempt to continue the boot. Data Field: Physical location of the I/O chipset.

During boot, firmware has found a hot-plug I/O slot with an incorrect default power state. The slot power should be off by default. Data Field: Physical location of the I/O slot.

Firmware encountered an error while attempting to power on an I/O slot. Firmware will deconfigure the I/O slot and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the I/O slot.

An I/O slot's standby (Vaux) power has failed. Firmware will deconfigure the I/O slot and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the failed I/O slot.

An I/O host bridge or hot-plug controller reported an illegal PCI[X] bus mode for its bus or slot, respectively. Firmware will deconfigure the I/O host bridge or I/O slot and display the following EFI warning, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the failed I/O host bridge or the failed I/O slot.

Firmware attempted to configure an I/O controller rope to an unsupported frequency. Firmware will deconfigure any I/O host bridge connected to the rope and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the failed rope.

Firmware has found an unsupported I/O host bridge type. Firmware will deconfigure the I/O host bridge and display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the I/O host bridge.

A Machine Check has been initiated

There has been a problem building the Memory Data Table (MDT).

There has been a problem building the Memory Data Table (MDT).

Memory page 0 was slated for deallocation in the PDT. EFI cannot launch with page 0 bad, so the system will halt.

There has been a problem building the Memory Data Table (MDT).

There has been a media failure.

Indicates that the chipset register test has failed. The data field contains the physical address of the failing register.

After FW's first access to main memory, FW detected that the CEC logged an error after reading back what was just written.

A DIMM that is required to be loaded in order for this DIMM to function properly is not loaded, so FW will deallocate this DIMM. Currently, none of the platforms require any DIMMs to be loaded in order for this DIMM to work properly.

The DIMM specified by the physical location has an SPD EEPROM that has a bad checksum. The Data field is the physical location of the DIMM.

Detected a error in DIMM SPD

A DIMM was installed whose DIMM type is not compatible with the current set of supported DIMMs for this platform.

The DIMM type of this DIMM is not the same as the other DIMMs in the same group. The group of DIMMs is deallocated. If this is the last active group of DIMMs in the system, the system is halted.

The DIMM type table is full

An entry for the DIMM was not found in the DMT table. The data field contains the DMT entry that the caller wanted to find (in Dimm number format, which is 2 bytes, upper byte is the extender number, lower byte is the chip select of the rank caller is looking for.)

The FW selftest of CEC multi-bit error (MBE) detection has failed. The upper 32 bits of the data field contain the Dword offset within the cacheline of the failed MBE detection. The lower 32 bits are split in two, and they contain the bit numbers within the Dword that were flipped in order to cause an MBE.

The FW selftest of CEC multi-bit error (MBE) signaling has failed. The upper 32 bits of the data field contain the Dword offset within the cacheline of the failed MBE detection. The lower 32 bits are split in two, and they contain the bit numbers within the Dword that were flipped in order to cause an MBE.

The FW selftest of CEC single-bit error (SBE) detection has failed. The data field contains the bit within the Dword that was flipped that caused the CEC to not see an SBE.

The FW selftest of CEC single-bit error (SBE) detection has failed. The data field contains the bit within the Dword that was flipped that caused the CEC to not see an SBE.

Memory FW detected errors below 1MB. FW will not allow boot in this case, so memory FW will reinterleave and retest.

Memory FW could not figure out which rank maps to the physical address specified in the data field.

Memory FW was unable to clear the platform error logs on the CEC. The Datafield contains the error status of the CEC.

Memory FW was unable to clear the platform error logs on the CEC. The Datafield contains the error status of the CEC.

The Error registers in the CEC have failed to clear. The data field contains the error status of the CEC after the attempted clear.

A DIMM that is required to be loaded in order for this DIMM to function properly is not loaded, so FW will deallocate this DIMM. Currently, none of the platforms require any DIMMs to be loaded in order for this DIMM to work properly.

An error occurred that memory FW does not know how to handle.

The memory interleaving code failed.

FW was unable to create a memory configuration with no errors in low memory to hand off to EFI.

A series of MEM_MBE_IN_RANK chassis code will be sent when an error is detected by firmware. The data fields will contain information on the error based on the data type as follows: Physical Location - location of dimm(s) in error; Physical Address - address affect by error; Syndrome - Firmware generated ECC syndrome that can be used to further isolate the error.

The chipset's memory controller failed the register test. The data field contains the address of the register that failed selftest.

Memory Discovery could not detect any DIMMs installed.

FW could not continue because there are no valid memory ranks loaded.

The PDT has been disabled, and FW found memory errors during selftest. This is a stopboot condition. Also, the PDT will never be disabled in customer systems, so this event should never be seen in the field.

An event indicating that the user has the PDT disabled on this boot. The PDT will never be disabled in customer systems, so this event should never be seen in the field.

Error writing entry into the PDT.

An attempt was made to add an entry to a full PDT. The entry is not added, and this event is sent.

Memory FW was unable to save or restore the original error configuration (including CEC error log and signal enable and CPU ECC detection). This event should never be seen in the field unless there is a FW problem

The rank structure that corresponds to the rankID in the data field could not be found in the Rank table. The Data field is the rankID of the structure it is looking for. This error event should never be seen.

More than one error type was detected when only one error type was expected.

The forward progress bits that memory FW uses to track state are invalid. The data field is the fwd progress field.

The memory error status has bits set in it that indicate another non-memory error occurred. The data field contains the CEC's error status.

The memory test summary bits are invalid. The data field is the test summary bits.

Memory rank shadowing has been selected but is not supported by the revision of the memory controller.

The control bit to skip the DIMM distribution check is set and the DIMM distribution check was skipped. This bit should only be done in the factory and not in the field.

The control bit to skip the DIMM loading order check is set and the DIMM loading order check was skipped. This bit should only be done in the factory and not in the field.

The control bit to loop on destructive memory test is set and the destructive memory tests are run continuously. This bit should only be done in the factory and not in the field.

The control bit to skip the DIMM set check is set and the DIMM set check was skipped. This bit should only be done in the factory and not in the field.

The control bit to skip the DIMM SPD check is set and the checking of the DIMM SPD was skipped. This bit should only be done in the factory and not in the field.

The control bit to load an alternate memory configuration is set and an alternate memory configuration has been loaded. This bit should only be set in the factory and not in the field.

The OS_INIT vector has not been registered

The OS_MCA vector has not been registered

An Uncorrected Machine Check has occurred

A PDH register has failed.

The handler for SAL_CHECK has failed for an unknown reason.

The handler for SAL_INIT has failed for an unknown reason.

Indicates that FW encountered a Fatal interleaving error. The data field contains the return status from the interleaving procedure call.

Unexpected return to SAL_CHECK.

The SFW TOC vector (SAL_INIT) has been unexpectedly returned to.

Firmware is adding a device tree node for a CPU that is degraded in functionality. The cpu should not be trusted and will not be active in the system.

Firmware was unable to locate a required element in the device tree and cannot create a partition. The resource that cannot be located is listed as an ansi string in the data field.

The currently executing cell is not configured to be part of the cell set it is attempting to rendezvous with.

The current cell could not read a remote cells CSR. The remote cell number is displayed in the data field. These cells will not be able to rendezvous.

The currently executing cell arrived too late to rendezvous with the other cells described in the complex profile as cells it should rendezvous with.

The currently executing cell detected CPUs that are incompatible with it to be installed on a cell that the current cell is trying to rendezvous with.

The current cell was too slow creating the local rendezvous set and the other cells have left it behind. It will not be able to participate in the remainder of the rendezvous. The data field is unused, but the cell emitting this event is the one too late to rendezvous.

The reporting cell was not included in the final global set that was agreed upon. This means that another cell either could not reach the reporting cell or the reporting cell was too late arriving to a required state.

No cells in the PD can be a core cell. This is fatal.

System Firmware was unable to notify utilities of the selected core cell number.

The fabric code is unable to find a service provider for a required banyan service.

The fabric port specified in the data field had an error.

An error occurred reading a CSR. The CSR address is displayed in the data field.

Error writing to Fabric. CSR data in data field.

Incompatible crossbar slices are installed The data field is the two revisions reported by slice1 and slice0 of the CSR data. Bits [31:0] slice0 revision Bits [63:32] slice1 revision

Crossbar slices are in different locations. The data field is the two locations reported by slice1 and slice0 of the CSR data.

A CPU has taken over as the monarch CPU.

SRAM cannot be accessed on the cell board. Execution cannot continue.

The PDH Arbiter component/chip cannot be located or used.

A required piece of PDH bus hardware cannot be contacted.

The physical location of the PCI controller with mixed speeds is displayed in the data field.

During walking of the IO busses, the maximum depth was exceeded. This is a hardware configuration problem. The data field contains the physical location.

A Timeout occurred during RI initialization. The CSR is in the data field. The alert level will vary.

SuperIO has been detected in the PCI slot displayed in the data field.

IO Link Software error was corrected.

Parity error in Reg FIFO Internal parity error.

TLB Fetch timeout.

Link presence goes away, FE.

LBA to SBA parity error on command, rope will go fatal.

Access to invalid TLB entry Requesting rope fatal.

Memory Fetch Timeout.

An error was encountered when initing the rope number specified in the data field.

LBA correctable timeout error was encountered.

LBA uncorrectable Function Error was encountered.

LBA uncorrectable Timeout Error was encountered.

Misc uncorrectable error discovered on LBA.

LBA encountered an uncorrectable parity error.

LBA misc. Fatal Error encountered.

LBA Fatal function error encountered.

LBA Fatal Parity error encountered.

LBA Fatal timeout error encountered.

Misc Uncorrectable Error encountered on the card specified in the data field.

Misc fatal error was discovered on the PCI card specified in the data field.

The calculated and compared Checksums of the SPD EEPROM don't match.

The Options component encountered a header checksum error. The actual data is in the data field of the chassis code.

The Options service data had a bad checksum. Actual data is in the data field.

Internal inconsistency in the interleave tables.

The CellInfoList is not null and was expected to be. There has been an error in interleaving.

Error in constructing the Memory Descriptor.

Unable to update the local memory layout.

A required address was not found within a mapped address in the PDT.

Failure to install a partition level PDT. Errors prevented it.

A critical resource that is required early in the initialization process either could not be found, or was unusable. The specific resource is specified in the data field as follows: Platform Parameters Component not found in FIT: 0xdead0001; SRAM_BASE not found in platform parms: 0xdead0002; SRAM_SIZE not found in Platform Parms: 0xdead0003; firmware framework not found in the fit: 0xdead0004; Framework Segment not usable: 0xdead0005; bad NVRAM: 0xdead0006; PDH Arbiter unusable: 0xdead0007; SRAM unusable: 0xdead0008; CPU unusable: 0xdead0009; Options Component Unusable: 0xdead000a; Real Time Clock unusable: DEAD_RTC; Unknown: 0xdead0086

An internal firmware error was encountered. This is usually caused by a bad parameter passed to a function, corrupt memory, corrupt malloc tables or something similar. The data field contains the IP address of the function that encountered the error.

NVRAM failed with a data compare error. 3 chassis codes will be sent. The first one will have the expected data and the second the actual data and the third one will be the address.

An NVRAM CRC Error was detected. There will always be 2 chassis codes sent. The first one will give the expected data and the second the actual data.

Get Error Response Mode has been called. The first 8 bytes of the response mode string are displayed in the data field and must be converted to ASCII from the hex values.

The required semaphore could not be obtained due to errors. The data field contains the IP of the routine trying to obtain the semaphore. A request was placed for more NVRAM to be allocated but NVRAM was full.

The NVRAM block requested has an unexpected revision. This chassis code will be emitted in pairs. The first one will contain the expected revision number, the second will contain the actual revision number.

The requested NVRAM block was not found. The ID that was not found is displayed in the data field.

The block id specified in the data field is locked.

Firmware tried to unlock a NVRAM block that was already unlocked. Data field contains the block ID.

The header in the NVRAM space was not found.

The Freelist used vor Non-Volatile Memory allocation is corrpt.

System firmware has detected a condition that requires the cell to be reset for reconfiguration. The function has been called and is now executing. Data field contains the cell number being reset.

During PD rendezvous, system firmware encountered a problem sending commands to the utilities system. This will prevent a fully functional PD from being created.

System Firmware has determined that cell or system progress must be halted. The data field contains the Instruction Pointer of the function that called for the halt. The second instance of this code being emitted indicates the major state in system change. This code must be emitted in pairs.

The DUI (Developers User Interface) was entered, but there is no console available for the interface.

During Error processing and reporting, an error was detected that prevented further processing of errors. The data field contains an ASCII message indicating the problem.

System firmware is unable to complete the request to reset the cell for reconfiguration. Typically, are required step has not been performed yet or a needed resource is unavailable.

The cell was not able to reach all the other cells in its configured set through the fabric. The data field contains the bitmask of actual cells that were reached.

Firmware detected a PCI-to-PCI bridge that exceeds the maximum supported bridge depth. Firmware will not configure I/O devices below the maximum bridge depth. Such I/O devices will not be usable as console nor boot devices but might be usable by the O/S. Data Field: PCI function address of the bridge that exceeded the maximum depth limit. Bits 24..31: segment number Bits 16..23: bus number Bits 11..15: device number Bits 8..10: function number Bits 0..7: reserved (0)

Debugging event, not for release. This event is no longer used on Everest/xPeak systems but its event ID is still contained in the code base.

This event is unused

The reporting cell read an unknown state from a remote cell. This chassis code will be emitted in pairs. The first one indicating the cell number in the data field and the second code indicating the state read in the data field.

The reporting Cell thinks that it should be the core cell but has discovered another cell in the same PD that thinks it should be the core cell. This is a serious problem.

The utilities system firmware component received an error response from the SINC in response to a command being sent. The exact error is displayed in the data field. Typically, this can occur when the SINC cannot talk to the MP.

System Firmware issued the Retrieve Cell Slot State command to the Sync and got an error back. See related chassis code or the specifics of the error.

This denotes the fact that all the cpus in the cell did not rendezvous.

This chassis code indicates that the cell does not have any access to a PD.

This indicates the cell would not be able to join the other cells in the PD level rendezvous. The data portion represents the cell id of the cell that incurred the loss of lockstep.

This indicates that some of the cells did not show up during the PD level rendezvous.

This indicates that catastrophic errors have been found in the PIN block of the cell controller. The cell needs to be reset/ halt.

This means that the cell monach cpu has not completed the assigned task within the timeout and hence it will be deconfigured.

This indicates that the cell is too late for the PD level rendezvous. And hence it will not join the other PD cells.

This indicates the state where the PD monarch was not able to complete the task within a certain time. It failed.

System firmware on the Core cell was unable to update a slave cell with the location of the root of the partition tree. The CPU that was unable to be contacted is printed in the data field.

Read test on a CSR failed and the CSR contents were not updated. This chassis code will be emitted in 3's, with the CSR Address, expected data, and actual data given.

This chassis code reports the failure in collecting the ICM parameters needed for the cell interleaving.

This chassis code indicates that the cell interleaving routine could not get the information on the cell memory.

This chassis code is used to represent the failure in updating the GNI information of the cell with the CLM ( cell local memory) information obtained from the Complex Profile.

This represents the failure in adjusting the memory information with the minimum ZI requirements.

Complex Profile A (Stable Profile) stored checksum does not match the calculated checksum. The expected data and actual data are displayed in the 2 reporting event Ids.

The Dynamic Complex Profile (Group B) stored checksum did not equal the calculated checksum. The Expected Data and Actual date are displayed in successive chassis codes.

The stored value of the complex profile Group C does not match the calculated value. Expected data and actual data are stored in successive chassis codes.

The Complex Profile Group A sequence ID is invalid. Booting cannot continue. The actual data is in the chassis code data field.

The Dynamic Complex Profile (Group B) sequence ID is invalid. The invalid Sequence ID is displayed in the data field.

The Group C Partition Complex Profile Sequence ID is invalid. The value read is displayed in the data field.

An internal EFI firmware error was encountered. This is usually caused by a bad parameter passed to a function, corrupt memory, corrupt malloc, corrupt firmware tree or something similar. The data field contains the IP address of the function that encountered the error.

The Complex Profile Group A PD assignment for this cell does not match the PD or Partition number in Group C of the complex profile. This is a fatal condition for the cell. The PD number from group A will be emitted first, followed by a subsequent code for the PD assigned in group C.

The Partition (PD) assigned to this cell in the complex profile group A and C is larger than the maximum allowed number of PDs as specified by Group A.

Tried to obtain the port semaphore but GetPortSemaphore returned an ERROR. Could be a failed write to the port semaphore crossbar CSR or another cell owned the semaphore. Data field bits 32:63 contain the crossbar ID and bits 0:31 contain the port number for which the semaphore was being obtained.

Currently owned the port semaphore but could not release the semaphore. Data field bits 32:63 contain the crossbar ID and bits 0:32 contain the port number.

There was an error reading from the BMC token when attempting to write to SAL NVM. This is a stop boot condition. Data: Lower 32 bits, BMC Token Number. Upper 32 bits, bmc return status.

The read from SAL NVM has failed. This is a stop boot condition. Data: The token number on which the read failed

There was an error when trying to write to a BMC Token. This is a boot warning condition. Data: lower 32 bits are BMC token number, upper 32 bits is the status return from the BMC.

There has been an error writing the BMC_FIRST_BOOT token. This is a stop boot condition.

The read of a FRU has failed. Data: Device ID of device that failed the FRU read.

The read of a FRU has failed the checksum test. Data: Device ID of device that failed the FRU read.

The read of a FRU has failed due to a version problem. Data: Device ID of device that failed the FRU read.

A ROM Rev and FIT Rev do not match. Data: Code for what didn't match: 0x1 = PAL_A, 0x2 = PAL_B, 0x4 = SAL_A, 0x8 = ACPI, 0xA = EFI

A ROM Rev and Rev Block do not match. Data: Code for what didn't match: 0x3 = PAL, 0x5 = SAL_A, 0x7 = SAL_B, 0x9 = ACPI, 0xB = EFI, 0xC = BMC

The FIT is bad.

The FIT is bad.

PAL_A_ROM has generated a warning.

PAL_B_ROM has generated a warning.

Firmware tried to default the Dynamic (Group B) complex profile and encountered an error.

An I/O device (or host bridge) detected a bus parity error. An I/O device (or host bridge) mastered a bus transaction and received a parity error response from the target. Data Field: Physical location of the I/O device (or host bridge).

An I/O device (or host bridge) detected an internal error. An I/O device (or host bridge) detected a bus error. Data Field: Physical location of the I/O device (or host bridge).

Firmware has deconfigured an I/O host bridge due to an error (see earlier error event). Firmware will display the following EFI warning message, 'Failed I/O slot(s) deconfigured.' Data Field: Physical location of the deconfigured I/O host bridge.

Firmware tried to default the Partition (Group C) complex profile and encountered an error.

The Reporting Cell is not configured to be in a PD, according to Complex Profile Group A.

DIMMs are not loaded on the extender in a thermally optimal way. Boot is still possible, but the DIMM arrangement should be changed to the loading order recommended in the users manual. The data field indicates the number of the extender with incorrectly loaded DIMMs.

Not enough cells made the Rendezvous for boot to continue. The rules are listed in the cause action section.

SFW's INIT handler failed to rendezvous the processors.

SFW's Machine Check Handler was unable to log or clear I/O error registers.

Cannot escalate an MCA to BERR

Cannot escalate an MCA to BINIT.

SFW failed to get the feature set from PAL.

PAL Failed to rendezvous the processors during a MCA.

SFW failed to get the feature set from PAL.

SFW's MCA Handler has failed to rendezvous all the slaves Data: Return from the rendezvous call.

A bad rendezvous vector has been registered.

No Machine Check Monarch exists, exiting MC Rendezvous.

The OS has not registered a wake-up mechanism for rendezvous.

PAL call failed to set the BINIT escalation bit

The PAL call PAL_GET_FEATURES has failed.

The PAL call PAL_SET_FEATURES has failed.

An internal SAL_ABI firmware error was encountered. This is usually caused by a bad parameter passed to a function, corrupt memory, corrupt malloc, corrupt firmware tree or something similar. The data field contains the IP address of the function that encountered the error.

The Memory extenders have not been loaded in the correct order.

The length field within the ESI (Extensible SAL Interface) table does not agree with the product of the entry_count field and the size of each entry. Data Field: computed value of the length based on entry_count and size of the entries.

The computed checksum for the ESI (Extensible SAL Interface) table is not zero as expected. EFI is halting. Data Field: the computed checksum.

EFI found an unsupported entry type within the ESI (Extensible SAL Interface) Table. Data Field: unknown type.

EFI was attempting to output a GUID in the EFI_GUID_HALF1 and EFI_GUID_HALF2 events which was larger than 128 bits. The data field contains the actual length of the GUID in bytes.

EFI is halting. Look for the cause of the halt in preceding events. Data Field: the 'halt' (0x0F) major change in system state code.

This code will be sent when FW detects a rank installed in the system that doesn't support chipspare. The data field is used to indicate the rank that the x8 DIMMs are installed. It is in the format 0x00000000XDXCXBXA or 0x00000000YBYAXBXA where X and Y are the number of the rank.

EFI has detected an internal error. The actual error is unspecified by this event. Examine previous events and console output for possible explanations.

EFI has executed the 'break' shell command. EFI is halting. The 'break' command is currently implemented as an infinite loop to halt EFI.

The EFI USB interrupt service has detected the host controller is hung. EFI is halting.

The EFI/SAL handoff structure's version does not match EFI expectations. EFI is halting. Look for EFI_SAL_HANDOFF_VER_EXPECTED to provide EFI's expected value. Data Field: Actual value of the version in the structure.

EFI is unable to obtain access to all the RTC (Real Time Clock) SAL services. This means that EFI is unable to fully interact with the RTC. EFI is halting. Data Field: Return status from internal EFI function.

EFI is unable to obtain access to all the SAL timer services. This means that EFI is unable to fully interact with the timer. EFI is halting. Data Field: Return status from internal EFI function.

EFI is unable to start the periodic timer. This timer interrupts EFI periodically to process time sensitive events. EFI is halting. Data Field: Return status for internal EFI function.

EFI did not find an I/O port space region in the MDT. EFI is halting.

EFI reached an unimplemented section of code. EFI is halting. Data Field: Unique identifier indicating the location reached within the code.

EFI was unable to read the current speedy boot settings. The speedy boot settings are stored within the BMC. EFI will use a default value of 0 and continue booting. The speedy boot functionality is also accessed via the boot test EFI shell command and via the OS. These other accesses will likely fail. Data Field: Return status from internal EFI function..

A SAL Callback was attempted. This is not permitted. EFI is halting. Data Field: index of the function that was being called.

While attempting to calibrate the EFI stall timer, system firmware is unable to determine the frequency of the CPU interval timer. System firmware will assume 800 MHz for the purpose of the stall timer calibration and continue boot. Data Field: error status code (should be 0xFFFFFFFD).

The EFI system events have already been initialized. This is unexpected. EFI is continuing. Data Field: the current value of the system event entry point.

EFI was unable to create an internal virtualization event while initializing EFI's System Events (IPMI events). This internal event is not an IPMI event; rather it serves as a trigger for EFI to virtualize the System Event facility when going virtual. EFI will likely halt. Data Field: return status from internal EFI function.

An error was detected while initializing the FPGA node and services associated with the PDH.

Firmware encountered an error when creating the ioconfig node as a child of the pdh node.

System firmware was unable to correctly set up the pdh arbiter node as a child of the pdh node, or was unable to locate and attach the pdh arbiter service to the node. The status is returned in the data field.

The PDH service was unable to either get or set the property specified in the data field as an ASCII message.

PDH encountered an error creating the ACPI Hardware Node in the device tree or installing its properties.

The PDH service encountered an error while creating the ipmi node or adding properties to it. The status is in the data field.

Installed processors are not of compatible models or families

Processors with different cache sizes are installed

SFW is selecting a new monarch processor due to compatibility problems.

The monarch stepping is not equal to the lowest installed CPU stepping.

A CPU's FSB frequency is overclocked. Data: Local CPU Number.

There was an error reading the info ROM area of the CPU. Data: CPU Physical location

PAL_A has not been executed and control has been transferred back to SAL_B.

PAL_B has not been executed and control has been transferred back to SAL_B.

Data: Lower 32 bits have Local CPU Number

Data: Monarch's Local CPU Number

Supplemental tests have been run on the cpus in the node and an error was encountered. If this event id is only emitted once, then the cpu detected that it failed on its own and the offending CPU id is in the data field. If the event is emitted three times, then the monarch CPU on the cell detected the error and the offending CPU id, expected data and actual data are reported in the data field of the three events.

While reading a XBC CSR, a multi-bit error was found. Data field includes the CSR data that includes the error. A previous event, FABRIC_READ_ERROR, details the CSR address that failed.

The return value from a function was an unknown value. Data field is the unknown status that was returned.

EFI queries the BMC on the system board for the status of a system ID. The BMC could not complete the request successfully or on time. Data Field: Internal EFI function status.

BMC reported a system ID status as inaccessible, reported invalid status or cannot return the current value of a system ID. Data Field: uuid status or internal EFI function status. System ID status: a 1 byte value 0 extended to 64bits: 0x00 -> primary and secondary values are valid 0x01 -> primary and secondary values are magic 0x02 -> primary and secondary values are inaccessible 0x04 -> primary and secondary values are invalid 0x08 -> primary and secondary values are null (UUID only) 0x10 -> primary and secondary values are different, value (primary or secondary) is valid 0x11 -> primary and secondary values are different, value (primary or secondary) is magic 0x12 -> primary and secondary values are different, value (primary or secondary) is inaccessible 0x14 -> primary and secondary values are different, value (primary or secondary) is invalid 0x18 -> primary and secondary values are different, value (primary or secondary) is null (UUID only)

Firmware tried to write a primary or secondary system ID as requested by the user during the boot sequence. The write failed. Data Field: Internal EFI function status.

The system ID(s) currently in the system is either invalid or, if the EFI_SYSID_BMC_WARNING, EFI_SYSID_BMC_READ_ERROR or EFI_SYSID_BMC_WRITE_ERROR events are also present, inaccessible to the system firmware. A stop boot condition will be generated and software license will probably be invalid. Data Field: 64-bit value. If preceded by 0xbad00000000000 the following valid values are possible: 0000 -> valid UUID (should never see this one) 0001 -> magic UUID 0002 -> inaccessible UUID 0004 -> invalid (bad CRC) UUID If zero, then one of the following conditions occurred: Invalid combination of primary and secondary system ID values User declined copying/entering system ID values when prompted by firmware All other values indicate failure during attempt to update system IDs.

EFI is unable to find the SAL services for installing interrupt handlers. EFI was trying to install the run-time handlers that are required for normal EFI booting. EFI will be halting. Data Field: internal EFI function status.

EFI is unable to find the SAL service to install run-time interrupt handlers. These handlers are required for normal EFI booting. EFI will be halting. Data Field: internal EFI function status.

EFI is unable to find the SAL services for installing interrupt handlers. EFI was trying to install the boot-time handlers that are required for normal EFI booting. EFI will be halting. Data Field: internal EFI function status.

EFI is unable to find the SAL service to install boot-time interrupt handlers. These handlers are required for normal EFI booting. EFI will be halting. Data Field: internal EFI function status.

Too many parameters were passed in a request for the utilities system to perform an operation. No more data is provided.

A crossbar port is expected to be present, but its presence detect bit is not set. Data field bits 32:43 contain the crossbar ID, bits 44:55 contain the port number for which the error occurred, and bits 0:31 contain the port status information.

A crossbar port is expected to have its HW_LINK_OK bit set, but it is not. Data field bits 32:43 contain the crossbar ID, bits 44:55 contain the port number for which the error occurred, and bits 0:31 contain the port status information.

A connected crossbar port was found to have its FE bit set. Data field bits 32:43 contain the crossbar ID, bits 44:55 contain the port number for which the error occurred, and bits 0:31 contain the port status information.

There was an error while initializing the Cell Controller-Xbc interface. The data field contains the address of the Cell Controller CSR for which the error occurred.

The CC - XBC link failed to initialize.

EFI is unable to determine current system mode. The EFI/SAL interface is not initialized. This interface should have been initialized before now. This event indicates an internal EFI error. EFI will continue executing.

The BMC has returned an invalid system mode. Data Field: the invalid mode. Expected values are 0 or 1.

EFI is unable to specify a new system mode. The EFI/SAL interface point is not initialized. This interface should have been initialized before now. This event indicates an internal EFI error. EFI will continue executing in the current mode.

EFI is unable to enter normal system mode. The EFI/SAL interface is not initialized. This interface should have been initialized before now. This event indicates an internal EFI error. EFI will continue executing in the current mode.

EFI is unable to initialize part of the SAL/EFI interface. This crucial service provides access to certain BMC functionality such as the security system. EFI will halt. Data Field: Return status from internal EFI function.

A needed tree node was not found. The data field contains the ASCII name of the tree node that was not found.

EFI is unable to modify the system state from 'booting' to 'running'. This is done as part of Exit Boot Services. The system will not be able to enter a sleep mode. Data Field: For errors, this data is zero. For warnings, this data indicates the current system state as: 0 Error 1 booting 2 running 3 attention 4 fault 5 booting + attention

CPUBusConfigValue setting in options as been compared with what is reported by PAL as settable and CPUBusConfigValue is specifying at least one bit that is not supported by this version of PAL using the Get Processor Bus Dependent Configuration Features. This chassis code is emitted in pairs, the first data field contains the PAL expected values; the second data field contains the requested setting from options.

Firmware was unable to correctly issue the Get Processor Bus Dependent Configuration Features command.

A pair of DIMMs installed in the system are mismatched, and that pair of DIMMs will not be used. The data field indicates which pair of DIMMs are mismatched in the format 0x000000000000XBXA where X is the number of the rank that is mismatched.

EFI is unable to initialize internal library. This collection of internal services is required for much of EFI's functionality. EFI is halting.

EFI is unable to initialize the security level. The privilege level of the system may or may not be Admin. It is likely certain EFI facilities will be unavailable. EFI will continue booting but security may be compromised. Data Field: Return status from internal EFI function.

EFI detected an invalid value for its internal privilege level. This value is stored within SAL. EFI will continue but system security may be compromised. Data Field: The invalid privilege level.

EFI detected an invalid privilege level when setting a BMC password. Only the levels of Admin (0x30) and User (0x20) are permitted. Data Field: the invalid privilege level.

SFW has determined that the Memory Data Table (MDT) table is invalid.

Processor has incompatible fixed core ratio. Data: Local CPU Number.

Data: A bitmask for which CPUs are slated to be deconfigured

An error occurred while reading a crossbar remote route table, or an unexpected/invalid value was read from the table. The data field consists of the crossbar ID (32:43), the port number of which the table was read (44:55), and the return status of the read call (0:32).

An error occurred while trying to read the PORT[n]_NEIGHBOR_INFO crossbar CSR. The data field consists of the crossbar ID (32:43) and port number (44:55) for which the CSR was read.

A quad of DIMMs installed in the system are mismatched, and that quad of DIMMs will not be used. The data field indicates which quad of DIMMs are mismatched in the format 0x00000000XDXCXBXA where X is the number of the rank that is mismatched.

The DIMM at the physical location given by the data field had excessive errors and has been marked as 'FAILED' by firmware.

A XBC port was expected to be functional, but its OE bit was not set. The data field consists of the contents of the port_status CSR (0:31), the XBC number (32:43), and the port number (44:55).

Unable to read the PORT_STATUS CSR for a XBC port. The data field consists of the contents of the PORT_STATUS CSR (0:31), the XBC number (32:43), and the port number (44:55).

A XBC port was unexpectedly found to be landmined. The data field consists of the XBC number (32:43) and the port number (44:55).

Reporting cell tried to rendezvous with a cell with processors that are running at a different speed. The data field lists the offending cell

The link between the local CC and the local XBC is unexpectedly not initialized. The data field is the XIN_LINK_STATE CC CSR value.

A value that was expected to be a XBC number was found to be an invalid XBC number. The data field is the invalid XBC number.

A value that was expected to be a valid XBC port number was found to be invalid. The data field is the XBC number (33:44) and the invalid XBC port number (44:55).

A bad parameter was passed to the utilities function that manipulates the LED on replaceable parts. The offending parameter is displayed in the data field.

A neighbor type read from a XBC PORT_NEIGHBOR_INFO CSR was different than the expected neighbor type. This event is emitted twice, first with expected data and second with actual data. Data field 1: XBC number (43:32), XBC port number (55:44), expected type (31:0) Data field 2: XBC number (43:32), XBC port number (55:44), actual neighbor type (31:0).

A XBC port number was unexpectedly found to not be a valid XBC-CC port. The data field consists of the XBC number (32:43) and the port number (44:55).

A XBC port was unexpectedly found to be an invalid XBC-XBC port. The data field consists of the XBC number (32:43) and the port number (44:55).

The XBC neighbor chip number does not match the expected value for this topology. The data field contains the expected neighbor chip number (32:63) and the actual neighbor chip number (0:31).

The XBC neighbor port number does not match the expected value for this topology. The data field contains the expected neighbor port number (32:63) and the actual neighbor port number (0:31).

A write to a BMC token has failed. This is a boot warning condition. Data: Upper 32 bits, BMC failure return code. Lower 32 bits, BMC token number that failed.

The utilities system reported an error while trying to carry out the command to turn on, flash or turn off the LED. The status returned by the command is displayed in the data field.

2 cpus think that they have the same ID within the cell. Typically this would mean that PAL reported the same cpu id for more than 1 cpu on a bus. The cpuid is in the data field.

OS crashdump started (D700)

OS legacy PA hex fault code (Bxxx). Possible I/O error or system panic

A memory dump occurred on the system, or on one partition in a cellular system. The dump occurred due to either a non-recoverable error or by user request. EFxx is the OS dump status (the success/failure of the writing of the dump). EF00 = success (followed by either EF0A = successful dump with sync, or EF09 = successful dump without sync), EFFF = a general error, EFFE = dump path assertion failure, EFFD = no dump was taken by default, choice or failure, EFFC = dump was aborted by user.

SFW has failed to set the processor timeout value via a PAL call. Data: PAL call return value.

During EFI security initialization, the attempt to determine what privilege level a blank password provides, failed. Most likely this indicates the BMC has failed. EFI assumes that the BMC has failed and will attempt to continue booting. Some EFI functionality may be unavailable. Data Field: Return status from internal EFI function.

As part of normal security initialization, EFI attempted to issue a close session to the BMC (I.e. force the BMC to GUEST mode). This attempt failed. EFI is unable to initialize the security system. EFI will continue but security may be compromised. Data Field: Return status from internal EFI function.

As part of normal security initialization, EFI attempted to issue an open session to the BMC in order to raise the privilege level to the highest permitted by a blank password. This attempt failed. EFI is unable to initialize the security system. Data Field: Return status from internal EFI function.

As part of normal security initialization, EFI attempted to record the current privilege level. This attempt failed. EFI is unable to initialize the security system. Data Field: Return status from internal EFI function.

As part of normal security initialization, EFI attempted to record the current privilege level. This attempt failed with a privilege violation error. EFI is unable to initialize the security system. Data Field: Return status from internal EFI function.

OS dump, error writing image area to disk (E055)

Early in bootstrap, the coherency controller (CC) registers are checked for Deadlock Recovery Reset. This chassis code indicates that CC logs will be stored to NVRAM.

SFW detected a memory address parity error. The data field contains the physical location of DIMM that saw the parity error.

The loading order of the DIMMs is incorrect. The cell is halted.

Timeout Waiting for SDRAM parts to become ready - mem_status[0] Refresh Control Register

The version of Memory extender installed in the system has not been qualified to work with the version of the baseboard installed in the system.

There is a fabric topology mismatch with the XBCs in the complex. Data Field: (Topology of XBC << 32) | Topology of destination XBC 0x00 Topology not yet determined 0x30 Domelight 0x40 U-Turn (Left cabinet) 0x41 U-Turn (Right cabinet) 0x42 Cross-Flex 0x43 U-Turn

While routing the XBC to XBC ports, an invalid port was encountered. The data field is the crossbar number (32:43) and the port number (44:55).

The XBC could not get neighbor information. Data Field: XBC # << 32 | internal port attempting to access neighbor

For the XBC being routed, routing has already been attempted, but an error occurred. Inspect chassis codes from other cells for more details regarding the nature of the problem. The data field consists of the XBC number (32:63)

This means that the error event log cannot be logged to the persistent storage. The data field gives the event type that was supposed to be logged.

An XBC port was found to have an unexpected error. The data field consists of the crossbar number (32:63) and the current port errors (0:31)

During fabric routing a port on a XBC was found in error or had been previously marked as in error. PDC will route around this XBC port. Data Field: XBC number (32:63) and external XBC port number (0:31)

Data field: the unexpected forward progress state (0:31) XBC number (32:44) Cell number (56:63)

A crossbar was found to be in an unexpected forward progress state during fabric routing. This crossbar stayed in the unexpected state until Fabric Discovery timed out. Data field: unexpected forward progress (0:31) XBC number (32:44) Cell number (56:63)

An XBC port was found that is not healthy. This indicates at least one of the following about the port: - Hardware link is not okay - Presence detect is false - Fatal error detected - SBE detected - LPE detected - Port landmined The data field of the chassis code indicates which port is unhealthy, as well as the fabric routing state before the problem was encountered.

The CC to XBC link is not viable.

There was a problem performing remote routing on the local XBC. Chassis codes sent before this one may provide more details about the exact nature of the problem. The data field consists of the XBC number that failed routing (32:63)

Two or more XBC-XBC links were found to be broken. The data field is the XBC number (32:63) and a bit map of the ports broken (0:31)

After unlocking the XBC Global Semaphore for a takeover, this cell did not get the semaphore.

When a cell holds an XBC semaphore for an extended period of time, fabric will attempt to takeover the semaphore so that the rest of the cells will have access to it. Fabric will attempt to take the SM4 for a period of time. If it is unable to unlock the SM4 within the timeout period, it will send this chassis code and halt the cell. Data field: XBC number (32:63) and current owner (cell) of the semaphore (0:31)

During Fabric Discovery, the cell will wait until it gets the XBC's Global Semaphore. It waits for a very long time. This chassis code indicates that the wait has timed out.

The XBC Release Semaphore timeout is designed to fail last. The semaphore could not be released. Any other cell (even outside the PD) may be blocked because the XBC is a global resource. Data field: current semaphore owner (0:31) XBC number (32:43) port number (44:55) cell number (56:63)

Management Processor Firmware detected improper data in NVRAM (bad checksums.) Either the NVRAM layout changed, or the Management Processor Battery may not be maintaining the data through A/C power cycles.

Management Processor Firmware detected a software error and is logging an event. The data represents data associated with the error seen.

An I2C Communication failure with the Baseboard Management Controller was detected. Without I2C communication, the system cannot be powered on/off or reset.

A stored CRC value did not match the calculated CRC value for the specified address.

See Summary.

2 cpus in the system are reporting different revisions. This event will be emitted in groups of 3 with the two revisions reported in the first 2 data fields and the cpu number in the 3rd data field.

This chassis code will be emitted in pairs. 2 cpus are reporting that they are running at different frequencies. The two frequencies are reported in the data fields.

The rating for the cpu and the actual speed will be emitted in 2 sequential event data fields.

The complex profile is stored in NVRAM on the MP and each cell. All copies must match. For this error to be generated, not only is the MP's copy of the complex profile invalid, but not all of the cell's copies match.

The MP detected 2 or more cabinets with the same cabinet number.

The complex identification information in group A of the complex profile is invalid. The MP (Manageability Processor) command 'ID' must be run. The SSKEY hardware is required.

The battery on the SBCH is below the safe threshold. The battery can be replaced online.

The partition is being reset because its watchdog timer expired and automatic restart is enabled.

The processor dependent hardware controller (PDHC) on the cell board had its watchdog timer expire. The PDHC will reset the watchdog as the main program runs. If the watchdog does not get reset within 7 seconds the timer will expire, resetting the PDHC.

The Cabinet Power Up request was aborted due to ambient air over temperature.

The power requirements for the cabinet exceeds the capabilities of the available Bulk Power Supplies. The PM3 section of the Utilities Subsystems keeps a tally of the power requirements for all installed entities in a cabinet. The power available from the Bulk Power Supplies does not meet the requirements of the installed entities, according to the Cabinet Power Tally.

When given a power up request, the cabinet had to abort the start up due to less than the required number of Cabinet Blowers installed.

When given a power up request, the cabinet had to abort the start up due to less than the required number of IO fans present.

The AC power connected to the PDCA (Power Distribution Control Assembly) was removed. The data field contains the physical location of the PDCA. The PDCA source that was deleted can be identified by the implementation dependent field (data byte 3) of the physical location: data byte[3]: 0 for PDCA 0, 1 for PDCA 1.

A cabinet main blower has failed. Depending on the number of blowers still operating, the cabinet may or may not shut down. View the Error Log entries to determine if the cabinet is operating. If many log entries call out entities powering off during the same time frame as this BLOWR_FAIL, the cabinet has probably shutdown. Carefully review the log for the first few events within the same time frame for the root cause of the problem. The GSP command, PS, will show a detailed power status for a cabinet. If the +48V LED on the Front Panel Board is not lit, power is not enabled to the cabinet. This is an indication the cabinet blowers have probably gone from N to N - 1 status requiring an immediate cabinet shutdown.

A 48 Volt DC Converter powered by the specified PDCA failed on the designated Bulk Power Supply. The PDCA powering the converter on the BPS that failed can be identified by the implementation dependent field (data byte 3) of the BPS' physical location: data byte[3]: 0 for PDCA 0, 1 for PDCA 1.

The designated Bulk Power Supply is reporting its fan has failed.

The 48 Volt DC Converter powered by the specified PDCA in the designated Bulk Power Supply, is in over temp condition. The PDCA powering the converter on the BPS that failed can be identified by the activity status (last byte of chassis code): e = PDCA 1 f = PDCA 0

The number of functioning Bulk Power Supplies has decreased to where the Cabinet Power supplied (number of available Bulk Power Supplies times power output per each) minus the estimated Cabinet Power consumed is greater than 0, but less than the output of one Bulk Power Supply.

The PM has detected the value of +48V power, as measured on the UGUY board, has exceeded an upper threshold.

The PM has detected the value of +48V power, as measured on the UGUY board, has fallen below a lower threshold.

A cabinet fan has failed. Depending on the number of cabinet fans still operating, the cabinet may or may not shut down. View the Error Log entries to determine if the cabinet is operating.

Housekeeping power has exceeded expected levels.

Housekeeping power has fallen below expected levels.

Through failures or reconfiguration, the BPS for the cabinet named are illegally configured. There must be a BPS connected to each phase of the power. Phase 1 feeds BPS slots 0 & 1, phase 2 feeds slots 2 & 3, and phase 3 feeds 4 & 5. There must be a BPS connected to each phase. If 4 BPS are installed in a cabinet in slots 0 - 3 and 4 & 5 were empty, this would be an illegal configuration. They should be installed in 0,1,2,and 4 or 0,1,3,and 5 or some combination thereof. The PDCA physical location determines which phase is configured incorrectly. Data Byte 3 (implementation dependent field) indicates the PDCA number used when the configuration error occurred:

A Bulk Power Supply is reporting an unknown BPS ID. The Bulk Power Supply will not be powered up and added to the Power Available tally. If cabinet is not powered up, it will refuse to power up until this fault is corrected.

The cabinet's Ambient Air Sensor detected a change in air temperature entering the over-temp-high range. The Cabinet will be shutting itself down to prevent component damage.

The cabinet's Ambient Air Sensor detected a change in air temperature crossing to the low range. The air temperature may be rising or falling. This is just a reporting of entering the over-temp-low range.

The cabinet's Ambient Air Sensor detected a change in air temperature crossing to the mid range. The air temperature may be rising or falling. This is just a reporting of entering the over-temp-mid range..

An IO Chassis cooling fan has failed. Depending on the number of fans still operating, the cabinet may or may not shut down. View Error Log entries to determine if the cabinet is operating. If many log entries call out entities powering off during the same time frame as this IOFAN_FAIL, the cabinet has probably shutdown. Carefully review the log for the first few events within the same time frame for the root cause of the problem. The Guardian Service Processor command, PS, will show a detailed power status for a cabinet. The +48V LED on the Front Panel Board not lit, power is not enabled to the cabinet, indicating the cabinet IO Chassis fans have probably gone from N to N - 1 status requiring an immediate cabinet shutdown.

This code is issued when the Cabinet Power supplied (number of Bulk Power Supplies times power output per each) minus the estimated Cabinet Power consumed drops below 0. Utilities firmware will not allow a cabinet in this state to power up (see ABORT_PWRUP_BPS). Utilities firmware will not shut down a cabinet in this state. However, there is a possibility of a cabinet brownout, making the cabinet unreliable.

After a BLOWR_FAIL, there were N-1 blowers functioning. This is an illegal condition causing immediate cabinet shutdown to prevent component damage.

After a IOFAN_FAIL, there were N-1 fans functioning. This is an illegal condition causing immediate cabinet shutdown to prevent component damage.

One of two fans in the Utility chassis of the IO Expansion Cabinet has failed.

The Watchdog Timer checks for inactivity, or hung state, of the Cabinet Level Utilities (CLU) portion of the UGUY. During activity, the timer is continually reset. If the timer expires, it will automatically reset the CLU microprocessor. This will not affect running partitions.

An invalid checksum was received when reading the FRUID EEPROM for the device named in the chassis code. If this is a single error, the fault lies with the named FRU. If there are many INVALID_CKSM entries in the Event Log, there is probably a problem with the I2C bus.

One or more of the System Backplane Power Boards is reporting a DC Fault through the System Backplane Local Power Monitor. The physical location of the failing power board is in the Data Field of the event.

An attempt to read the EEPROM (FRUID) on the IO Backplane Board failed.

An attempt to read the EEPROM (FRUID) on the IO Backplane Power Board failed.

An attempt to read the Local Power Monitor Fault register on the IO Backplane Power Board failed.

The Local Power Monitor of the named IO Chassis is reporting a Power Brick over temperature condition.

The Local Power Monitor on the named IO Chassis has reported a power fault condition.

The Local Power Monitor on the named IO Power Board failed to properly margin the power as commanded.

Either by command or as part of initialization, the data from a FRUID EEPROM failed a read command. This does not necessarily mean the FRU has failed, just that the FRUID data cannot be read.

Either by command or as part of initialization, the data from a FRUID EEPROM failed a read command. This does not necessarily mean the FRU has failed, just that the FRUID can't be read.

An attempt to read the EEPROM (FRUID) on the System Backplane failed

A read command on the system backplane I2C bus failed.

A write command on the system backplane I2C bus failed. The type of command that failed can be identified by the activity status field (last byte) of the encoded field. B = RC Cable Configuration Register write C = Backplane Voltage Margin Register write 9 = Flex circuit configuration register write

The Local Power Monitor on the named System Backplane has detected a power fault. The failing Backplane Power Board status is read from the Backplane LPM I2C interface register and the value is placed in the data field of the event (bits 15-8).

Margining voltage to the System Backplane has failed.

An attempt to write data to the FRUID EEPROM by the MFG level MP command WF failed. The FRU handle of the failing FRUID is embedded in the two uppermost bytes of the data field.

The fan on a CPU is not operating in a manner that provides enough air flow to cool the processor

The fan on a CPU is operating in a manner that provides enough air flow to cool the processor but is not at normal operation

The fan on a CC chip is not operating in a manner that provides enough air flow to cool the processor

The fan on a CC chip is operating in a manner that provides enough air flow to cool the processor but is not at normal operation

System FW and the PDHC have incompatible shared memory interface revisions. Data byte 0 is the PDHC's supported ICM revision number. Data byte 1 is System FW's supported ICM revision number.

The MP checked the FW revision of the PDHC identified in the physical location data field and discovered that it did not recognize the revision as one that it has been qualed with. This is an unsupported configuration.

The local Power Monitor is reporting a fault with the named Cell Power Board. The data field of this event can be decoded as follows where a bit set in any of the status fields indicates a fault: data byte 0: (power_good << 1) | (power_fault) data byte 1: Cell Power Board converters status bits[0:2] - memory power bricks 0-2 status bits[3:5] - power i/f bus bricks 0-2 status bits[6:7] - JAB core power bricks 0-1 status data byte 2: Cell converters status bit 0 - clock power status bit 1 - cache power status bit 2 - link power status bit 3 - CC core power status bit 4 - FSB power status bit 5 - 48-V status data byte 3: CPU module converters status bit 0 - CPU module 0 core power status bit 2 - CPU module 1 core power status bit 4 - CPU module 2 core power status bit 6 - CPU module 3 core power status

The CPU node retuned an error when calling its initialize node function. The specific status is displayed in the data field.

ExecuteCommand issues commands that execute on remote CPUs via IPI interrupts. If the command failed to execute, this event is printed and the data field contains the status.

A remote CPU is in a state where it cannot receive and execute a new command. The current status of the CPU is provided in the data field.

An error was encountered when executing a PAL_PROC. This code will be emitted in pairs. The Proc INDEX will be in the data of the first chassis code. The status is in the second data field.

CPUs not loaded in correct order. Correct loading order is CPU 0, 1, 2, 3.

The XBC logged a SBE or LPE after they should have been cleared. Either the clear failed, or a new error was logged immediately. Data field: XBC number (32:43), port number (44:55), port status information (0:31)

The CC to XBC Link pattern test failed. Data Field: This event will be emitted three times 1st event: XBC number (32:43), port number (44:55) 2nd event: expected pattern (0:63) 3rd event: actual data read (0:63)

System firmware was unable to complete a platform storage read command from the utilities system. The exact status printed in the data field.

System firmware was unable to complete a platform storage write command. The actual status is returned in the data field.

The Sequencer was unable to find the tree node it needed to complete an operation. The tree node is in the ASCII in the data field.

System firmware attempted to read a partition variable from the GSP and store it in options. An error was encountered during this process. The data field contains the partition variable element ID that was being processed.

One or more power converters on the Cell or Cell Power Board has reported a fault. However, because of redundancy in the power system, the power to the Cell is still good. The data field contains detailed power fault location information that is specific to each platform.

CPUProcConfigValue setting in options as been compared with what is reported by PAL as settable and CPUProcConfigValue is specifying at least one bit that is not supported by this version of PAL using the Get Processor Dependent Features. This chassis code is emitted in pairs, the first data field contains the PAL expected values; the second data field contains the requested setting from options.

System firmware was unable to successfully issue the PAL_GET_PROC_FEATURES PAL proc. The data field is unused

This event is a tool to aid in the debugging and testing of firmware.

The CLU has encountered an undefined case in its control flow.

The Cell voltage margin settings do not match the Normal, +5%, or -5% values.

For debug purposes, many assumptions made by the PDHC developer(s) are checked at run-time. If this event log is seen, it indicates that the hardware or software is in an unknown state. For developer debug purposes, the data field describes where in the code that the error was detected. Data Bytes[0-1]: The line number within the source code file where the error was detected. Data Bytes[2-7]: The first 6 characters of the source code file name.

An unknown error has been detected by the PDHC firmware. For developer debug purposes, the data field describes where in the code that the error was detected. Data Bytes[0-1]: The line number within the source code file where the error was detected. Data Bytes[2-7]: The first 6 characters of the source code file name.

An attempt to write to a device on the PDHC's I2C bus has failed. The devices on the I2C bus are the Cell's FRU EEPROM, the Cell Power Board's FRU EEPROM, the voltage margining D-to-A converters, and, if they are accessible, the CPU Module Power Pods' FRU EEPROMs. The Data field information contains information that can identify the exact device that has failed. Refer to the Cell ERS for a mapping of I2C device addresses to devices. Data Bytes[0-1]: Reserved Data Bytes[2-3]: I2C Device Address Data Bytes[4-5]: Starting Word Address Data Bytes[6-7]: Size of attempted access (in bytes).

An attempt to read from a device on the PDHC's I2C bus has failed. The devices on the I2C bus are the Cell's FRU EEPROM, the Cell Power Board's FRU EEPROM, the voltage margining D-to-A converters, and, if they are accessible, the CPU Module Power Pods' FRU EEPROMs. The Data field information contains information that can identify the exact device that has failed. Refer to the Cell ERS for a mapping of I2C device addresses to devices. Data Bytes[0-1]: Reserved Data Bytes[2-3]: I2C Device Address Data Bytes[4-5]: Starting Word Address Data Bytes[6-7]: Size of attempted access (in bytes).

An attempt to write to a device on the PDHC's SM bus has failed. The devices on the SM bus are the CPU modules' FRU EEPROMs, the CPU modules' Processor Information ROMs, and the CPU modules' thermal sensors. The Data field information contains information that can identify the exact device that has failed. Refer to the Cell ERS for a mapping of SM Bus device addresses to devices. Data Bytes[0-1]: Reserved Data Bytes[2-3]: SM bus Device Address Data Bytes[4-5]: Starting Word Address Data Bytes[6-7]: Size of attempted access (in bytes).

An attempt to read from a device on the PDHC's SM bus has failed. The devices on the SM bus are the CPU modules' FRU EEPROMs, the CPU modules' Processor Information ROMs, and the CPU modules' thermal sensors. The Data field information contains information that can identify the exact device that has failed. Refer to the Cell ERS for a mapping of SM Bus device addresses to devices. Data Bytes[0-1]: Reserved Data Bytes[2-3]: SM bus Device Address Data Bytes[4-5]: Starting Word Address Data Bytes[6-7]: Size of attempted access (in bytes).

The PDHC did not read valid frequency information from the CPU modules' or Cell's FRU EEPROMs, or the frequency registers would not update properly. Following this event, the Cell will not boot until the problem is corrected and Cell Power has been turned off, then on again, using the PE command.

An error has occurred while updating System FW. More details about the update failure may be available as displayed by the Firmware Update Utility (FWUU).

The PDHC firmware was reset for some unknown reason.

A hardware fault prevented the PDHC from configuring the thermal sensor(s) on one or more of the CPU modules. Following detection of this fault condition, the Cell will be prevented from booting until the Cell is powered 'off', then 'on', using the PE command.

A CPU module's temperature has exceed the high temperature threshold. As a result of this event, an irrevocable 2 minute timer will begin. At the end of 2 minutes, the offending CPU module will be powered off by the Cell hardware. The Cell must be powered off then on using the MP's PE command before the CPU module will be powered again.

An error occurred while updating the PDHC firmware. More specific details of the update error may be displayed by the Firmware Update utility running on the MP.

The cell type (IPF or PA) does not match System FW type. The cell type is detected based on information stored in CPU modules' FRUID EEPROMs. The System FW type is determined based on data that is embedded in the System FW ROM image. This is checked each time Cell power transitions from off to on, and each time the System FW is updated. Following the detection of this mismatch, the Cell will not be allowed to boot until the problem has been resolved.

This event is emitted after the PDHC has waited longer than a maximum expected time for the PDH arbiter to grant it control of the PDH bus. The PDHC will continue waiting for control of the PDH bus until the arbiter grants it control, or the Cell is powered off using the MP's PE command. While waiting for the PDH bus, the PDHC will NOT perform its normal duties such as monitoring the Cell status, and passing messages from the system to the MP, and the PDHC heartbeat will not blink.

This event is emitted after the PDHC has waited longer than a maximum expected time to obtain control of the PDH bus semaphore. The PDHC will continue waiting for control of the PDH bus semaphore until System FW relinquishes control of the semaphore, or the Cell is powered off using the MP's PE command. While waiting for the PDH bus semaphore, the PDHC will NOT perform its normal duties such as monitoring the Cell status, and passing messages from the system to the MP, and the PDHC heartbeat will not blink. The data field contains debug data that may be useful for developers. Data_byte[0] = last value read from PDHC's address for the microSemaphore register. Data_byte[1] = boolean indicator (1=set,0=not_set) of whether the PDHC's flag is set. Data_byte[2] = boolean indicator (1=set,0=not_set) of whether the System FW's flag is set.

This event indicates that an error occurred while transmitting an IPMI message in the BMC2HOST direction. The data field contains more detailed information about the source of the error. Data Bytes 0 & 1 form a 16-bit IPMI error indicator that has the following values and meanings: 1 - IPMI_HOST_BUSY_TIMEOUT - The PDHC could not put a message in the BMC2HOST hardware message queue for over 10 seconds, so the pending message(s) were dropped. 2 - IPMI_INVALID_MSG_SIZE - The MP sent an IPMI message response that has an embedded size indicator that is less than 4 bytes or greater than the size of the message data. The poorly formed message response will be dropped. 3 - IPMI_BMC2HOST_Q_FULL - The BMC2HOST message queue in the PDHC is full, so a message response from the MP has been dropped.

EFI was unable to read the initial debug level from the BMC token. EFI will continue with an unknown value for the debug level. Data Field: Return status from internal EFI function.

A XBC port was unexpectedly found to not be landmined. The data field consists of the XBC number (32:43) and the port number (44:55).

The number of landmined XBC ports was not within the allowable range. There is a minimum number of landmined ports because some ports are always unused. There is a maximum number of landmined ports because there is a limit to the number of broken links allowed in a system. The data field shows the number of landmined ports found

Data field contains the backplane type found. During Intra SKD Routing, the backplane type detected was either a Medel backplane or was unrecognized. The backplane could therefore not be routed. This is a firmware sanity check. Data Field: system type

Prior to initializing the CC to XBC link, the XIN error mask should be zeroed out to prevent spurious errors from interfering with the link initialization. This write to zero out the error mask failed. Data Field: (cell << 56) | return status

The Coherency Controller's (CC) XIN link did not initialize properly. The data field contains the return status from an attempted read of the CC Primary Error Mode CSR. (0 = SUCCESS)

The Coherency Controller's (CC) XIN link did not initialize properly. The data field contains the data read from the CC Primary Error Mode CSR.

The Coherency Controller's (CC) XIN link did not initialize properly. The data field contains the return status from an attempted read of the CC Primary Error Mode CSR. (0 = SUCCESS)

The Coherency Controller's (CC) XIN link did not initialize properly. The data field contains the data read from the CC Error Mask CSR.

The neighbor's port connected to the link being crossed is not routable. This was the first attempt to cross the link, PDC will now look for another link it can cross. DATA: (xbcNum << 32 ) | (port << 44)

Fabric read error. Data field: (XBC number << 32 | return status)

Too many crossbar links are broken. Cell cannot boot, halting. Data field: XBC number << 32

For debug purposes, many assumptions made by the PM developer(s) are checked at run-time. If this event log is seen, it will either indicate that the hardware is in a unknown state that is not handled by the PM, or that a programming bug has been found. For developer debug purposes, the data field describes where in the code that the error was detected. Data Bytes[0-1]: The line number within the source code file where the error was detected. Data Bytes[2-7]: The first 6 characters of the source code file name.

An unknown error has been detected by the PM firmware. For developer debug purposes, the data field describes where in the code that the error was detected. Data Bytes[0-1]: The line number within the source code file where the error was detected. Data Bytes[2-7]: The first 6 characters of the source code file name.

This event is a tool to aid in the debugging and testing of firmware.

Failed link testing to ensure that SBE and LPE errors are detected properly by the XBC. The XBC did not detect any errors. Data field indicates the return status: (1 = err detected, 0 = no err detected, -1 = XBC accesses failed)

The data field contains the cabinet number that is invalid

The cell indicated in the data field is at a different firmware revision than the reporting cell. This is determined by evaluating the checksums of the 2 rom images.

An attempt to write to a device on the PM's I2C bus has failed. The Data field contains information that can identify the exact device that has failed. Refer to the UGUY ERS for a mapping of I2C device addresses to devices. Data Bytes[0-1]: Reserved Data Bytes[2-3]: I2C Device Address Data Bytes[4-5]: Starting Word Address Data Bytes[6-7]: Size of attempted access (in bytes).

An attempt to read from a device on the PM's I2C bus has failed. This event is only emitted when the PM is reading a BPS's. The Data field contains information that can identify the exact device that has failed. Refer to the UGUY ERS for a mapping of I2C device addresses to devices. Data Bytes[0-1]: Reserved Data Bytes[2-3]: I2C Device Address (to convert to BPS slot number subtract 1 and divide by 2) Data Bytes[4-5]: Starting Word Address Data Bytes[6-7]: Size of attempted access (in bytes).

An error was encountered trying to obtain the data required for the cell information structure in ICM. The data field is an ASCII message that indicates the information that was not found.

An error was encountered establishing the slave cells use of the diva console.

An error was encountered trying to relocate the registry on a slave cell to point to the core cells main memory structures.

The Calculated CRC for the group C Partition Profile did not match the stored value. The expected value and the actual value will be emitted in 2 sequential chassis codes.

Not able to find a core cell in the PD during a global MCA error processing.

An unexpected error occurred while initializing the fabric. The firmware is not able to analyze this error. Clues to the cause of this error may be found in the IPMI forward progress log (FPL) either shortly before or after this log entry occurred. The FPL is available from the management processor using the 'sl' command. HP-UX also saves these logs in the /var/stm/logs/os directory, and they can be viewed using the slview utility.

An internal firmware error was encountered. This is usually caused by a bad parameter passed to a function, corrupt memory, corrupt malloc tables or something similar. The data field contains the IP address of the function that encountered the error.

During the on line addition of a cell the partition adding the cell has determined inconsistent data as to which cell is being added. The cell addition will be aborted and the partition will resume execution without the new cell.

An error occurred while reading the routing from the source cell's port on the source XBC. Data Field: (source cell << 56 | source XBC << 32)

OLA cell cannot be added because it has resources that are not compatible with those already in the partition. Data field specifies the physical location of the cell which is incompatible and on which the OLA was attempted. The preceding chassis code or codes should already have been emitted specifying what the actual incompatibility was. The OLA cell will NOT be added to the partition, and the existing partition should not be affected.

Root Cell attempted to OLA a cell which hung somewhere in the OLA process - the cell released from BIB but never made it to its final rendezvous state. Data field contains physical location of the hung OLA cell. The OLA cell will NOT be added to the partition, and the existing partition should not be affected.

Root cell attempted to OLA a cell that was never released from BIB. Data field contains the physical location of the cell that is being OLAD.

Partition attempted to OLA a cell in an unexpected Cell state. Data Field contains the unexpected cell state of the OLA cell. The OLA cell will NOT be added to the partition, and the existing partition should not be affected.

Root cell will emit this chassis code indicating the OLA cell could reach all cells in the alive set of the existing partition. Data field will contain the physical location of the OLA cell. This chassis code should immediately follow a chassis code indicating exactly which cell the OLA cell could not reach. The OLA cell will not be added to the partition and the partition will be unaffected.

CPU's of mixed maximum core frequencies are installed

The Cell Controller-XBC link initialization is having an intermittent failure. The data field contains the number of initialization sequences that failed before being successful.

PDC failed clearing the OLA steering bit in the PDH FPGA microstatus register. Data field contains the physical location of the cell with the failure. This can only happen on an OLA cell and will cause that cell to reset and not to join the existing partition.

The attempt to update the PD Addr Map to include OLA cell failed.

Attempt to update the partition PDT with OLA cell PDT data has failed.

Attempt to update the cell map to include the OLA Cell failed

Fabric Discovery's final attempt to initialize the local cell's CC to Crossbar Chip (XBC) link has failed. This cell cannot talk to the fabric. Data: link init state bit read from the CC Link State register

An internal firmware error was encountered. This is usually caused by a bad parameter passed to a function, corrupt memory, corrupt malloc tables or something similar. The data field contains the physical address that failed mapping to a virtual address

Failure while writing the XBC CSR containing the link status

Failure while reading the XBC CSR containing the link status

Fabric Discovery's attempt to initialize the local cell's CC to XBC link has failed. The link initialization sequence has an intermittent problem.

An error was encountered while attempting to create and initialize a PCI device node

An error was encountered while scanning the PCI bus

An error was encountered while attempting to initialize a P2P bridge

Insufficient IO Port space to support the PCI card

Insufficient MMIO space to support the PCI card requirements

An error was encountered while attempting to initialize the SBA node

An error was encountered while attempting to discover SBA hardware

An error was encountered while attempting to reset the SBA

An error was detected in the link between the CC and the I/O controller.

An SBA cable error has been detected

Identified the cell number that is connected to the chassis.

An error occurred while attempting to create or initialize an LBA node

An error was encountered while attempting to configure LBA rope bundling width

error code

An error occurred while attempting to clear an LBA error log register

An error was encountered while attempting to generate LBA error logs

An error was encountered while attempting to discover LBA hardware

An error occurred while attempting to configure the LBA hardware

An error was encountered while attempting to scan the PCI bus

An error was encountered while attempting to configure PCI config space

The OLA cell failed accessing the complex profile. Cell will send Failed to OLA message back to partition and then reboot itself. Existing partition will not be affected.

A Firmware tries to find a main memory block large enough meeting alignment requirements.

Cell started OLA but is not configured in the complex profile of the partition. Cell will reboot to SINC_BIB. Existing partition will not be affected.

The Options service received an error when attempting to allocate an NVRAM storage block. Either an error was returned from the call, or the call returned successfully yet an invalid address was returned.

A failure occurred on the OLA cell during the attempt to synchronize its real time clock with the clock(s) in the existing partition. Data field contains physical location of OLA cell.

Access to SAL error log procedure timed out because the log facility was busy processing a request from another CPU. Data field indicates the SAL procedure ID.

The PDH FPGA IPR is not cleared after a MAX_RD_CLR_IPR_TRIES on a cell. The Data Filed in the Cell number. See the next Chassis Code to see the MAX_RD_CLR_IPR_TRIES

Indicated the PDH FPGA IPR is not cleared after a number of PDC attempts. The Data Field contents the MAX_RD_CLR_IPR_TRIES. Please look at the previous Chassis Code to see the Cell number.

attempt to synchronize the Real-Time Clock of the OLA cell with the existing partition failed because the RTC on the core cell could not be read.

One or more dimms are missing from the echelon given in the data field. The dimms may not be installed or firmware was not able to detect the dimms.

The code that reads the port state (landmine vs. healthy) expects a XBC internal port number, it received bogus data. The port state cannot be read. Data Field: (port << 44) | (xbc num << 32)

The code that writes the port state (landmine vs. healthy) expects a XBC internal port number, it received bogus data. The port state cannot be read. Data Field: (port << 44) | (xbc num << 32)

The main backplane is reporting the LPM status as fault.

The IO backplane has reported a local power monitor fault.

System firmware was unable to default the complex profile

Firmware call to set processor feature resulted in an error.

This chassis code shows that the error log space in the NVRAM has not been allocated for the current error event. This will be emitted out whenever a error section is attempted to be logged without allocation of log space in NVRAM

This indicates that the error logs for a particular event type have reached the maximum allowed to be stored in the NVRAM. The event type is indicated in the data field.

System firmware has been invoked to perform a cell delete operation but no cell in the system appears to be ready for deletion.

The bulk power supply is overcurrent

Data: Bulk location.

Error Response Mode code attempted a malloc of heap space that failed.

The dimm in the physical location given by the data field is not supported on this platform. The dimm may not be supported by the hardware, or the dimm may not have been properly qualified for this platform.

The OPTIONS component was unable to allocate NVRAM memory in order to store a non-volatile variable. The storage area for NVRAM options may be full, or there may be undetected corruption.

A dimm or CPU has failed and is not operational for the system. This event is emitted prior to determining if the cell should be integrated into the Partition.

A cpu or dimm error has been detected, and the Complex Profile, Cell Integration Table, Cell integration policy says to not integrate the cell into the PD. The data field is unused, but the cell that emitted this event is the one that did not get integrated.

The IO error context is corrupt. This will impair IO error reporting.

A rope went fatal from the SBA to the LBA. If all the ropes go fatal the IO subsystem is dead. Any I/O below the rope will not be accessible. The data field gives the physical location of the rope that went fatal. Some ROPE_FATAL conditions will not cause the system to go down. For Example, a rope that has gone fatal during an OLAR operation will only cause warnings to the user, not bring the partition down.

A PCI bus on the system is fatal. Any device on this bus is unavailable. Firmware was unable to complete card initialization due to an error. Data field contains physical location of failed bus.

One of the rope units in the SBA failed. If all of the rope units fail, then IO will not be available on this cell.

The System Flash Write Enable bit is incorrectly set and now clearing by PDC. The Data field contains the value of PDH Miscellaneous Signal Register read before System Flash bit is cleared.

System firmware encountered an error while trying to perform an operation during system initialization. This event ID will always be emitted before an event ID that describes the status of the operation that failed.

This means that all the cpus in the cell did not show up.

This means that all the cells did not rendezvous during the PD rendezvous. The data part will contain the Expected data and the actual mask of the cells that rendezvoused.

The FW tree sanity check failed during the MCA error processing.

This means that the registry sanity check failed during MCA error handling.

This means that MCA occurred while OS_MCA was performing error recovery.

This means that memory dump will be abandoned due to work-around for CN2272. This happens when one of the Blocking timeout in the Processor input block of the Cell Controller occurs.

The firmware tree is not complete and hence there will be no PD rendezvous.

The firmware parameter that defines the ACPI configuration is inconsistent in at least one of the cells in the partition.

Writing the XIN_ERR_ORDER_STATUS register of the CC failed. This is some sort of a hardware failure. Data Field: return status

An unexpected error occurred while initializing the fabric. The firmware is not able to analyze this error. Clues to the cause of this error may be found in the IPMI forward progress log (FPL) either shortly before or after this log entry occurred. The FPL is available from the management processor using the 'sl' command. HP-UX also saves these logs in the /var/stm/logs/os directory, and they can be viewed using the slview utility.

A value read by the PDHC from a CPU module's Processor Information ROM was not within acceptable limits.

An invalid parameter was specified when trying to set the cpu bus config register, cpu frequencies ratio field. Valid range is 0xe - 0x17

The overhead structure of the OPTIONS block in NVRAM has a checksum error.

During a cell OLA, the link on the local cell failed to initialize. Data Field: (my cell << 32) | XIN Link State

An attempt to disable the fabric link failed because writing the CC CSR failed. Data Field: (cell << 56) | return status

Could not determine the system type in order to write the appropriate error mask for the fabric link. Data Field: system type

Failed writing the XIN error mask for CC's fabric link. Data Field: (cell << 56) | return status

Could not read the XIN Link error mask register. Data Field: (cell << 56) | return status

The CC to CC link initialization sequence has failed. Data Field: link init status

An error occurred while trying to notify the MP that a reset is about to occur (QPartitionReleaseBIB command). The status is in the data field.

A fabric access error occurred while trying to disable the CC to CC link on a single cell Medel system. This cell will halt. Data field: error status

While updating the Port State register, the cell could not get the XBC semaphore. Data field is: (Port Num << 44 | XBC num << 32 | return status). Where return status is: (0 Success; -1 Access Failure; -2 Semaphore Owned By Another, -3 Semaphore Already Owned; -4 XBC Key Contention)

While updating the Port State register, the cell could not get the XBC semaphore. Data field is: (Port Num << 44 | XBC num << 32 | return status). Where return status is: (0 Success; -1 Generic Failure)

An unexpected error occurred while initializing the fabric. The firmware is not able to analyze this error. Clues to the cause of this error may be found in the IPMI forward progress log (FPL) either shortly before or after this log entry occurred. The FPL is available from the management processor using the 'sl' command. HP-UX also saves these logs in the /var/stm/logs/os directory, and they can be viewed using the slview utility.

While attempting to initialize the XIN link, it was found to already be initialized. A firmware assertion has failed. The link will not be re-initialized and processing should continue as normal. However, the system could be confused at this point.

The PDHC FW could not detect any CPU modules on its Cell board, so it is holding the Cell in reset.

The Cell has been disabled by PDHC FW because the CPU modules are not compatible. Compatibility is determined based on data stored in the Scratch/FRUID EEPROM on each CPU module. The CPU module partition compatibility byte for each CPU module must be identical.

The Cell has been disabled because of invalid data in a CPU module Scratch EEPROM. PDHC FW checksums the FRUID data stored in each CPU module's Scratch EEPROM. If a checksum fails, the Cell is held in reset and will not boot. The data field identifies the CPU module that failed.

The battery voltage level is low for the cell. This indicates that the NVRAM will not be saved if the power is removed.

There was an error while copying the routing for the XBC to the local XBC port. The cell will reset. Data: (XBC port << 44) | (XBC num << 32) | return status

The read immediately after a write while copying routing registers failed. Data: whether or not the XBC Key was enabled

Failed to release a XBC Semaphore while marking each XBC in the complex to indicate that routing has completed. Data: (XBC num << 32) | return value

Writing this XBC's forward progress register failed. Data: (XBC num << 32) | return value

Failed to get a XBC Semaphore while marking each XBC in the complex to indicate that routing has completed. Skipping this XBC. Data: (XBC num << 32) | return value

Reading this XBC's topology register failed. Data Field: (xbc num << 32) | return status

Could not check the traversability between two cells on an XBCless platform. Data field: return status (1 = SUCCESS, 0 = FALSE, -1 = FAILURE)

Could not check the traversability between two cells on an XBCless platform. Data field: return status (1 = SUCCESS, 0 = FALSE, -1 = FAILURE)

While checking traversability of a 2 cell back to back system, there was an error reading the local cell's XIN block. Data Field: return status (1 or -1)

While checking traversability of a 2 cell back to back system, there was an error reading the local cell's XIN block. Data Field: return status (1 or -1)

Could not traverse to the target cell. The XIN link is either not initialized, or is not connected to the target cell. However, the target cell is designated to be within the partition. Data Field: target cell << 56 | XIN link state register

Could not traverse to the target cell. The XIN link is either not initialized, or is not connected to the target cell. However, the target cell is designated to be within the partition. Data Field: target cell << 56 | XIN link state register

Error reading the XIN_LINK_STATE register of the CC. This occurred while verifying that the link had been disabled. Data Field: cell being read << 56 | return status from the CSR read.

Failure while reading the XBC CSR containing the link status. This occurred while attempting the retry process to get XBC to CC link initialized. Data Field: link init status

An unexpected error occurred while initializing the fabric. The firmware is not able to analyze this error. Clues to the cause of this error may be found in the IPMI forward progress log (FPL) either shortly before or after this log entry occurred. The FPL is available from the management processor using the 'sl' command. HP-UX also saves these logs in the /var/stm/logs/os directory, and they can be viewed using the slview utility.

The CPU that just completed self tests is functionally or performance restricted. The data field contains the Self Test State Parameter. The 2-bit state field (bits 1..0) can have the following values when this event is displayed: 01 - Performance Restricted - cpu still functions 10 - Functionally Restricted - cpu doesn't function properly

The RTC was found to be invalid and has been cleared

System firmware requested that Late Self Tests be run by PAL, but PAL returned that the tests did not actually run on the processor. The data field indicates the status word returned by PAL.

An attempt to update the cell state has failed due to a fabric crossbar failure. The cell number being updated in bits 63:56, while the traversable cell set (those cells connected to the fabric) is returned in bits 31:0

Failed to reset a cell due to an error setting the cell's state. The cell will not be reset with the other cells in the PD. The cell number is reported in the data field.

SFW has detected that a DRAM is failing on the DIMM specified by the physical location. The rank the failing DIMM is part of will be deallocated.

Internal CPU clocks are not valid when compared with the real time clock. The data field contains the hex value of the elapsed time. If this value is off a small percentage from the expected value (which is given in the next chassis code), the event is emitted.

Could not traverse the fabric to the cell being added. Data field: (chosen cell << 56) | return status, where -1 = failure

A XBC port was found to be unhealthy on this reboot. This cell will attempt to route around it. Data field: (local Cell << 56) | (local internal Port << 44) | (local XBC << 32) | XBC internal port number being routed around.

Error getting the XBC port's expected neighbor from a firmware table. Data field: 0 (SUCCESS) or -1 (FAILURE)

Either PDC is going to halt the cell or reset the partition because PDC was unable to access the PDH memory of either its local cell or another cell in the partition. The data field contains the error return value from PDC function IsHCellCpuDeconfig().

Either PDC is going to halt the cell or reset the partition because PDC was unable to access the PDH memory of either its local cell or another cell in the partition. The data field contains the error return value from PDC function SleepAndWakeupCountersGet().

Either PDC is going to halt the cell or reset the partition because PDC was unable to access the PDH memory of either its local cell or another cell in the partition. The data field contains the error return value from PDC function PdhGetHCellStructAddr().

Either PDC is going to halt the cell or reset the partition because PDC was unable to access the PDH memory of either its local cell or another cell in the partition. The data field contains the error return value from PDC function HasCpuCompletedWakeupTask().

Either PDC is going to halt the cell or reset the partition because PDC was unable to access the PDH memory of either its local cell or another cell in the partition. The data field contains the error return value from PDC function PdhGetHCellStructAddr().

There is a need to reset the cell for reconfiguration, but it cannot be done yet because the cell has not reported at BIB. The Reset is being scheduled to be performed later.

When processing the complex profile, the an unexpected 'Architecture Type' was specified in the PA/IA Arch field. The actual data found is displayed.

While trying to determine whether or not a particular processor has completed the task for which it was awakened, PDC was unable to access the deconfig byte information about the target processor. A processor should always be able to access this data in PDH memory for any processor on its own cell and for any processor on a cell that is alive in the partition. Therefore, PDC is either going to halt the cell or reset the partition because of this problem. The data field contains the PDC error return status from IsHCellCpuDeconfig().

While trying to determine whether or not a particular processor has completed the task for which it was awakened, PDC was unable to access the CPU's sleep and wakeup counters for the target processor. A processor should always be able to access this data in PDH memory for any processor on its own cell and for any processor on a cell that is alive in the partition. Therefore, PDC is either going to halt the cell or reset the partition because of this problem. The data field contains the PDC error return status from SleepAndWakeupCountersGet().

While trying to determine whether or not a particular processor has completed the task for which it was awakened, PDC was unable to access the CPU's forward progress state (i.e. PST state) for the target processor. A processor should always be able to access this data in PDH memory for any processor on its own cell and for any processor on a cell that is alive in the partition. Therefore, PDC is either going to halt the cell or reset the partition because of this problem. The data field contains the PDC error return status from CpuFpSet().

While trying to determine whether or not a particular processor has completed the task for which it was awakened, PDC was unable to access the CPU's Forward Progress State (i.e. PST state) for the target processor. A processor should always be able to access this data in PDH memory for any processor on its own cell and for any processor on a cell that is alive in the partition. Therefore, PDC is either going to halt the cell or reset the partition because of this problem. The data field contains the PDC error return status from CpuFpSet().

At a certain point in PDC boot, all of the processors in the partition except the PD monarch are put into a sleep, and they remain there until they are awakened by the PD monarch, at which time they read an architected location in Page Zero to find out where to branch to. This gives the OS a mechanism by which to bring processors under its control and have it executing OS code. This chassis log is sent if and when a problem is detected by PDC regarding the contents in the Page Zero location. This means that PDC cannot branch to the location logged in the Page Zero location. So, PDC sends this chassis log and then the processor returns to sleep. The data field is unused.

The Data Field contains the value used to determine a valid order.

While trying to get the sleep counter and the wakeup counter for a particular processor, which is kept in a data structure in PDH memory, PDC was unable to determine the address to the data structure on the remote cell. PDC is supposed to be able to calculate addresses to anything in PDH memory on other cells in the partition. The data field contains the PDC error return status from a function called PdhGetHCellStructAddr().

Error occurred accessing a PDC data structure. Depending upon the situation the cell or entire partition will be reset. The data field contains the return status for the function that encountered the error.

PDC is about to halt the cell because PDC was unable to determine the GNI address of the SlaveDispatcher function of PDC relocated to memory by PDC. The data field contains the error return value from the function GetGniCodeAddrFromRomCodeAddr().

PDC is about to halt the cell because at least one of the processors didn't complete the task for which they were awakened and then return to sleep. The data field contains an error return status.

PDC is about to halt the cell because PDC was unable to determine the GNI address of the CpuFpSet() function of PDC relocated to memory by PDC. The data field contains the error return value from the function GetGniCodeAddrFromRomCodeAddr().

PDC is about to halt the cell because one or more of the slaves were unable to change their CPU FP state in PDH memory on the local cell. The data field contains an error return status.

PDC was trying to move the cell monarchs on each of the non-core cells into the Dispatcher, but in order to do that, the PD monarch needs to be able to read the CPU number of the cell monarch on each of the non-core cells, which is kept in a data structure on each of the cells. PDC was unable to get the address to the CELL_CPU_STATE structure in PDH memory in a cell in the partition. The data field is the error return status from the PDC function called PdhGetHCellStructAddr().

PDC is about to reset the partition because at least one of the processors didn't complete the task for which they were awakened and then return to sleep. The data field contains the error return status from the PDC function CheckSingleSlave().

PDC is about to reset the partition because it is unable to determine the GNI address for the CpuFpSet() function for one or more of the cells in the partition. The data field contains the error return status from GetGniCodeAddrFromRomCodeAddr().

PDC is about to reset the partition because one or more of the processors were unable to successfully modify their CPU FP State (aka their PST state). The data field contains the error return status from the CpuFpSet() function.

MX2 initialization failed.

A cpu that is attached to a cpu that is slated for deconfiguration is being deconfigured as well.

FW failed to virtualize the mx2 interposer.

FW has failed to virtualize the mx2 interposer.

Installation of the FW PMI handler has failed.

Cell and or cpus have failed compatibility checks.

PDH space not available after release from reset.

MPON failed to release.

Dillon failed to reset.

DMD clock is not running.

All possible CPUs on a cell have been scheduled for deconfiguration.

A read error occurred while dumping the XBC port routing registers during boot. This cell will attempt fabricless boot. Data field: (XBC port << 48) | (XBC num << 32) | error status reg

After cell rendezvous for a 2 cell Medel, only one cell made it into the partition. Disabling the link failed. The cell will reset for reconfig. Data Field: return status

Power is no longer being supplied to input A0 on the cabinet specified in the data field.

Power is no longer being supplied to input A1 on the cabinet specified in the data field.

Power is no longer being supplied to input B0 on the cabinet specified in the data field.

Power is no longer being supplied to input B1 on the cabinet specified in the data field.

Failed to disable the XIN link init CSR on a XBCless system. Cell will halt. Data field: return status (0 = SUCCESS, -1 = FAILURE), -1 is expected for this event.

Error writing the XBC port's routing registers. The cell will reboot. Data Field: XBC port << 44 | XBC num << 32 | return status

Could not read the XIN error mask register on the CC. Data Field: cell number and return status

Could not write the XIN error mask register on the CC. Data Field: cell number and return status

While testing link traversability, a XBC CSR could not be read. Data Field: Port Number << 44 | XBC Number << 32 | return value

The Battery-Low interrupt was signaled in the Interrupt Pending Register in Dillon (PDH) by the hardware. PDHC is merely reporting the problem.

This means that the system FW MCA handler is not going to handoff to the OS_MCA handler.

When returning from other software, like when returning from ISL, PDC is trying to make sure that all of the slave processors in the partition are asleep; however, this event ID indicates that we were unable to access PDH memory of a cell that is supposed to be part of our partition. The data field contains the error return status from a function called SleepAndWakeupCountersGet().

When returning to PDC from other software, like returning from ISL, PDC tries to verify that all the slave processors are in the expected state (i.e. that all slave processors are asleep); however, this event ID indicates that at least one processor active in the partition was not asleep. So, PDC is going to reset the partition. The data field of this Event ID is the global CPU number of the first CPU in the partition not found in the expected state.

PDC could not access one of its own data structures on the local cell. The cell will be halted. The data field contains the return status from the PDC function that encountered the error.

The NVRAM-based descriptor for System Firmware NVRAM blocks is corrupt.

The cell will be reset because it was unable to access PDH memory on its own cell. While trying to move all the slave processors on the cell to the 'late boot sleep', the monarch tried to write the sleep timeout to PDH memory on its own cell, but encountered an error in doing so. The data field contains a PDC return status.

All CPUs have been determined to be manually deconfigured in NVM during boot. This may only happen when switching from single core CPU deconfiguration to multi-core CPU deconfiguration in product qualification testing. As a recovery, NVM settings have been changed to reconfigure all CPUs.

A failure has occurred trying to determine the number of CPU cores per module. Depending upon the situation, either the cell will be halted or the entire partition will be reset.

While writing the remote routing, the local XBC could not be accessed to determine the topology. Look for additional chassis codes to determine what will happen as a result of this failure. Data field: return status, either SUCCESS (0) or (-1)

Failed to route around a broken link on cell reboot. Data Field: PDC return status

Could not read the XBC register that contains the number of links that are currently broken on the complex. Data Field: (XBC Num << 32) | PDC return status

Could not read the XBC register that contains the number of links that are currently broken on the complex. Data Field: (XBC Num << 32) | PDC return status

Could not write the XBC register that contains the number of links that are currently broken on the complex. Data Field: (XBC Num << 32) | PDC return status

Could not read the XBC register that contains the number of links that are currently broken on the complex. Data Field: (XBC Num << 32) | PDC return status

Could not write the XBC register that contains the number of links that are currently broken on the complex. Data Field: (XBC Num << 32) | PDC return status

Too many broken crossbar links were found. This cell will have no connectivity to other cells in the complex. It will attempt a fabricless boot, except in a few configurations. Data Field: (XBC Num << 32) | number of broken links

Could not read the XBC register that contains the number of links that are currently broken on the complex. Data Field: PDC return status

Could not write the XBC register that contains the number of links that are currently broken on the complex. Data Field: (XBC Num << 32) | PDC return status

Could not read the XBC register that marks the ports that have been routed around. Data Field: (XBC Num << 32) | PDC return status

The PIOB route to the remote XBC was not traversable. The cell will halt. Data Field: (XBC Num << 32) | PDC return status

Could not release the remote XBC's semaphore. Cell will halt. Data Field: (XBC Num << 32) | PDC return status

Failed to complete a broadcast write to an XBC. Data Field: (XBC Num << 32) | PDC return status

Failed to complete a read to the built-in port of a XBC. Data Field: (XBC Num << 32) | PDC return status

Failed to complete a write to the local cell's port of the XBC. Data Field: (XBC Port << 44) | (XBC Num << 32) | PDC return status

The link between the CC and SBA failed meaning that I/O is not available to the reporting cell.

An error was detected in the SBA and the reporting cell has no I/O.

The structured exception handling within the system firmware failed during I/O initialization.

There is not enough malloc resources for the I/O structure exception handling. I/O on the reported cell is not available.

Error creating the structure for housing the I/O structured exception handling services and data. I/O is lost on the reporting cell.

Unable to bind the I/O structure exception handling to the internal data structures.

Error detected while initializing the I/O structure exception handling services.

Error initializing the I/O structure exception handling data structures.

The structured I/O exception handling data structures have an error. All I/O on the reporting cell is not available.

While setting up the internal SBA data and service an error was detected. All I/O for the reporting cell is not available.

An error attaching firmware services to the internal structures was detected. All I/O on the reporting cell is not available.

System firmware detected an error initializing internal SBA data structures and services. This is usually an error with unavailable resources.

The SBA type is unknown to the system firmware. The I/O on the reporting cell is not available.

An expected I/O device cannot be detected by the system firmware.

Too many broken links! The XBC port route around failed because the route-around port was bad too. Data field: (XBC port << 44) | (XBC num << 32) | port state

ECC (Error Checking and Correcting) memory is designed to detect and correct single-bit errors that occasionally occur in computer systems. This memory module is currently correcting many single bit errors.

Server Agents SNMP branch is not responding due to a portion of the IPMI Management Subsystem being locked by another entity.

A non-hot plug I/O slot's power consumption increases the total I/O power consumption beyond the supported limit. Firmware will display the following EFI error message, 'I/O configuration exceeds power limit' and disallow O/S boot. Data Field: Physical location of the I/O slot.

This is a warning that the system is running in a degraded mode. It will only be emitted in MFG mode when Memory SBE Seeding is enabled. This is only for testing of SBE seeding for LAB and possibly MFG use ONLY. It should NEVER be seen in the field.

Read failure while writing the number of failed links to the XBC. Data Field: Return Status (SUCCESS = 0, FAILURE = -1)

PDC could not access a complex profile. The partition will be reset because the available complex profile is not valid. Data field contains the return status from the function that encountered the error.

An unexpected error occurred while initializing the fabric. The firmware is not able to analyze this error. Clues to the cause of this error may be found in the IPMI forward progress log (FPL) either shortly before or after this log entry occurred. The FPL is available from the management processor using the 'sl' command. HP-UX also saves these logs in the /var/stm/logs/os directory, and they can be viewed using the slview utility.

PDC could not access a complex profile. The partition will be reset. Data field contains the return status from the function that encountered the error.

Before attempting a fabricless boot, the cell's link to the fabric should be disabled to provide isolation and stability. The link could not be disabled, so the cell will halt.

Configuration information on the processor was invalid. The cell will be halted. Data field contains the return value from the function that encountered the error.

The clock ratio that the processor is running at does not match the clock ratio that manageability is reporting.

The user has manually bypassed a stop boot condition (caused by an error during boot) and continued to boot an O/S. The system might experience unpredictable failures.

Firmware was unable to relocate the VGA BIOS to the hardcoded VGA BIOS region in main memory (physical address range 0xc0000 - 0xdffff). VGA routing has been disabled by firmware. No VGA device will be accessible on this boot.

The component compatibility matrix stored in NVRAM and used by system firmware has a checksum error. The stored value does not equal the calculated value. The data field will contain first the expected value, and the subsequent code will contain the actual data.

PDC could not read an internal CPU register. The partition will be reset. Data field is the return status from the function that encountered the error.

PDC could not read an internal CPU register. The partition will be reset. Data field is the return status from the function that encountered the error.

PDC failed reading a value out of its own copy of the internal CPU register settings. Data field is a status return indicating the type of failure.

PDC failed reading a value out of its own copy of the internal CPU register settings. Data field is a status return indicating the type of failure.

PDC attempted to update CPU registers to match their respective settings in the complex profile, but a failure was returned from the call to accomplish the update. Data field contains the failure.

PDC could not access a complex profile. The partition will be reset.. Data field contains the return status from the function that encountered the error.

PDC could not access a complex profile. The cell will be reset. Data field contains the return status from the function that encountered the error.

Could not find a potential core cell for the partition in the configured set. This cell will reset for reconfiguration. Data Field: return status from failing function

The potential core cell was not viable (i.e. no core I/O, etc). This cell will reset for reconfiguration. Data Field: bit mask of cells that made the rendezvous set

The potential core cell was not viable (i.e. no core I/O, etc). This cell will reset for reconfiguration. Data Field: bit mask of cells that made the rendezvous set

The potential core cell did not rendezvous with the rest of the partition. This cell cannot talk to the selected core cell. This cell will reset for reconfiguration. Data Field: bit mask of cells that made the rendezvous set

The local cell is disconnected from the rest of the system due to the main backplane configuration. While the partition is only configured to contain a single cell, the local cell is not a viable core cell. The cell will reset for reconfiguration. Data Field: bit mask of cells that made the rendezvous set

This cell has booted without the main backplane, probably due to prior main backplane errors. The partition it is in is configured with 3 or more cells. The combination of these two configurations is not allowed. The cell will reset for reconfiguration. Data Field: configured set

While validating the internal RTC data the data is read twice and compared. If the comparison fails to match the read is performed again up a maximum of 50 times. If we cannot get a match in 50 retries we issue this event.

PDC attempts to make sure that all of the cells in a partition are installed in the same processor architecture. PDC failed to read the architecture for another cell. PDC will reset all of the cells in the partition when this error is detected. The data field contains the physical location of the cell reporting the event.

The buffer size passed in to the XBC error logging routine through SAL_GET_STATE_INFO, SAL_CLEAR_STATE_INFO, or MCA logging is too small for the XBC error log Data field consists of: XBC number (32:43)

System firmware was unable to clear an XBC error. The data field contains: XBC number (32:43) port number (44:55) error type (0:31)

Error encountered while collecting PCI error logs. The result is some or all PCI error logs will be unavailable.

Error encountered while collecting SBA error logs. The result is some or all SBA error logs will be unavailable.

During fabric initialization, if a crossbar is found to be in an unexpected state, the number of retries is incremented. If the number of retries exceeds the maximum, then something is wrong and there is no way to initialize the fabric. Data field: number of retries (0:31), crossbar number (32:63)

ECC (Error Checking and Correcting) memory is designed to detect and correct single-bit errors that occasionally occur in computer systems. This memory module is currently correcting many single bit errors.

ECC (Error Checking and Correcting) memory is designed to detect and correct single-bit errors that occasionally occur in computer systems. This memory module is currently correcting many single bit errors.

A error occurred on the bus connecting the PCI card to the system bus.

A PCI card has been marked as 'fatal' by the operating system due to a bus error. The LBA has been isolated by the operating system due to an error which occurred in a device(s) connected to that LBA.

A PCI card has been marked as 'fatal' by the operating system due to a device error.

Firmware tried to read the first boot token an got a failure. The data field contains the token number that FW tried to read. This is a stop boot condition

monarch PA cell has detected that a cell it is attempting to rendezvous into its PD is not a PA cell and is thus incompatible.

A XBC error could not be cleared due to a write failure. The data field indicates the type of error: (XBC Port Num << 56) | (XBC Num << 32) | error status

Failed to read the XBC Global CSR Error Status register. Data Field: (XBC Port Num << 56) | (XBC Num << 32) | error status

The XBC CSR Low Severity error was not cleared or more errors remain. Data Field: (XBC Port Num << 56) | (XBC Num << 32) | contents of the XBC CSR Error Status Register

The XBC CSR High Severity error was not cleared or more errors remain. Data Field: (XBC Port Num << 56) | (XBC Num << 32) | contents of the XBC CSR Error Status Register

Failed to read the XBC Port Error Status register. Data Field: (XBC Port Num << 56) | (XBC Num << 32) | error status

Failed to read the XBC Global CSR Error Status register. Data Field: (XBC Port Num << 56) | error status